I would like to confirm my understanding of the GPIO setup on the MSP430 - as I am seeing behaviour that suggests that internal Timer A1 functionality takes priority over the GPIO selection for a specific pin.
I am using TI's sample application which is using Timer A1 as the source of System Time Scheduling – Timer A1 has a Compare OUT1 Output pin allocation at P2.2. Using an MSP430 Debugger, I see that the P2.2 Selection Register (P2SEL) bit is set to GPIO (Low), whilst the P2.2 Direction Register (P2DIR) bit is set to Input (Low). I also saw that Timer A1 TA1CCTL2 OUTMOD Register bits were set to 000b (OUT bit value) and the TA1CCTL2 OUT Register bit was set to 0b (low).
I planning to use P2.2(M2) as an input but however I noticed that P2.2 is permanently low.
Does the peripheral pin allocated to Timer A1 take priority over the GPIO selection for that specific pin – i.e.is P2.2 actually set to the Timer A1 OUT pin, instead of a GPIO Input pin?