Hi,
I have problem with MSP430F5338. I need set up timer to generate interrupt at the exact time. For example i need generate interrupt with frequency 1.5 , 2 , 2.5 , 3 , 3.5 (20,50-100Hz etc... ) Hz.
Now
Master clock is set up at 12MHz (used 12MHz crystal osc. - pins 7.2 - 7.3). This is ok i checked it on scope and logic analyzer. Divider for ACLK and SMCLK give me 6 and 3MHz - also checked.
Problem is : timer generate only 214kHz interrupt when TA0CCR0 = 1 and 68Hz when TA0CCR0 is anythink else (1-65535). I dont know what i am doing wrong.
Divider does not have the influence at timer frequency. I tried other timers -1A3 2A3 B0 - same result 68Hz and 
When i try basic PWM it was all normal, almost same setup, same clock and works fine on xx kHz.
this is my config :
static void s_sys_init_clock(void)
{
P3DIR |= BIT4; // SMCLK set out to pins
P3SEL |= BIT4;
// P1DIR |= BIT0; // ACLK set out to pins
// P1SEL |= BIT0;
P7SEL |= BIT2+BIT3; // Port select XT2
UCSCTL6 &= ~XT2OFF; // Enable XT2
UCSCTL3 |= SELREF_2; // FLLref = REFO
// Since LFXT1 is not used,
// sourcing FLL with LFXT1 can cause
// XT1OFFG flag to set
UCSCTL4 |= SELA_2; // ACLK=REFO,SMCLK=DCO,MCLK=DCO
// Loop until XT1,XT2 & DCO stabilizes - in this case loop until XT2 settles
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to
// expected frequency
UCSCTL4 |= SELS_5 + SELM_5 + SELA_5; // SMCLK=MCLK=XT2
UCSCTL5 |= DIVA__2 +DIVS__4;
}
#pragma vector=TIMER0_A0_VECTOR
__interrupt void TIMER0_A0_ISR(void)
{
if (P4OUT < 0x8F )// Toggle P1.0
{
//P1OUT ^= 0x01;
P4OUT ++;
}
else
{ P4OUT = 0x80;}
P3OUT ^= BIT0;
TA0CCTL0 &= ~ CCIFG;
}
and timer
TA0CTL |= TASSEL_2 + MC_1 + TACLR; // SMCLK + UP mode + timer clear TA0CCTL0 |= CCIE; // enable interrupt TA0CCR0 = 20000; // counter
I hope you understand my problem i am not eglish man.
thanks for any help