TimerB in CaptureMode : measure signal frequency

Hi,

New on MSP430 processors, I'm trying to use TimerB in Capture Mode on my board based on MSP430F247

Signal arrive on P4.0 and P4.1 pin, I want catch each rising edge in order to determine frequency

Here's my code : HW is OK, signal is arriving but I never go in TimerB interrupt : TimerB is running, Interrupt on TimerB is pending, but never go in interrupt code?

I'm working with CCS 6.1.0.00104

Do you have an idea, an example, or do you detect something strange in my following code?

My code use TimerA to generate 1ms timestamp, and I toogle P3.2 (Led) each 100ms (TimerA and Toggle Led works fine)

thanks

//***************************************************************************************

//***************************************************************************************

#include <msp430.h>                
unsigned int NbCycles100ms=0;

/** \brief Used to count 100ms periods */
    volatile unsigned int  tick_100ms;
    /** \brief Used to count 1ms periods and to generate other timings*/
    volatile unsigned int  tick_1ms;

    unsigned int Count_P40=0, R1Edge1=0, R1Edge2=0;
    unsigned int Count_P41=0, R2Edge1=0, R2Edge2=0;
    unsigned int overflow_count=0;
    unsigned int PeriodeP40=0, PeriodeP41=0;

int main(void) {
    unsigned int temp_u16, NbCycles100ms;

    WDTCTL = WDTPW | WDTHOLD;        // Stop watchdog timer

    //Clock configuration : External 8MHz Crystal on XT2 and ACLK = VLO
    BCSCTL1 = 0x0A; //XT2 = ON + XTS = LF + DIVA = 0 + RSELx = A
    BCSCTL2 = 0x88; //SELMx = 10 + DIVMx = 0 + SELS = 1 + DIVSx = 0 + DCOR = 0
    BCSCTL3 = 0xA0; //XT2Sx = 10 (3 to 16 MHz) + LFXT1S = 10 (VLOCK) + XCAPx = 00 + XT2OF = 0 + LFXT1OF = 0

    // stop everything
    TBCTL = 0;
    TBCCTL0 = 0; TBCCTL1 = 0; TBCCTL2 = 0; TBCCTL3 = 0; TBCCTL4 = 0; TBCCTL5 = 0; TBCCTL6 = 0;
    TBCCR0 = 0; TBCCR1 = 0; TBCCR2 = 0; TBCCR3 = 0; TBCCR4 = 0; TBCCR5 = 0; TBCCR6 = 0;

    // TimerA Init (1kHz base time)
    TACTL  = TASSEL_2 + TAIE;     // SMCLK, upmode, interrupt
    TACCR0 = 0x1F40;

    P3DIR |= 0x06;                    // Set P3.1 & P3.2 to output direction

    P4DIR = 0x0;  //As input
    P4SEL = 0x03; //Pin 4.1 et 4.0s special function enable

    // TimerB : input frequency measurement
    TBCTL = 0x0200;  // SMCLK + Continuous Mode + Interrupt Enable
    TBCCTL0 = 0x4000 + 0x1000 + 0x800 + 0x100 + 0x10; //rising edge + CCIxB + SCS + CAP + CCIE
    TBCCTL1 = 0x4000 + 0x1000 + 0x800 + 0x100 + 0x10; //rising edge + CCIxB + SCS + CAP + CCIE
    TBCTL &= ~0x1;    //Clear Interrupt
    TBCTL += 0x24; // TBCLR + MC_2 (continuous Mode)
    TACTL += 0x10; // MC_1 : up to TACCR0 value

    _BIS_SR(GIE); //Enable interrupts

    // Main loop
    while(1) {
        temp_u16 = tick_100ms;
        NbCycles100ms++;
        if (NbCycles100ms%2){
            P3OUT &= ~0x06;}
        else{
            P3OUT |= 0x02;}
        PeriodeP40 = R1Edge2 - R1Edge1;
        PeriodeP41 = R2Edge2 - R2Edge1;
        while (temp_u16 == tick_100ms){}; //Wait until end of current cycle
    }
}

#pragma vector = TIMERA1_VECTOR
__interrupt void Timer_A(void)
{
    switch( TAIV ){
        case  2: break;    //CCR1 not used
        case  4: break;    //CCR2 not used
        case 10: {

            tick_1ms += 1;

            if (tick_1ms == 99){
                tick_1ms    = 0;
                tick_100ms += 1;
            }
        } break;

        default: break;
    }
}
#pragma vector=TIMERB0_VECTOR
__interrupt void Timer_B0 (void)
{
      TBCCTL0 &= ~CCIFG;
      TBCTL &= ~0x1;
    //Capture detected
      if (!Count_P40)
          {
          // TBCCR0 = TBR; // Done automatically at ISR
          R1Edge1 = TBCCR0;
          Count_P40++;
          }
      else
          {
          R1Edge2 = TBCCR0;
          Count_P40=0x0;
          }
}
#pragma vector=TIMERB1_VECTOR
__interrupt void Timer_B1 (void)
{
  switch (TBIV)
  {
    //Capture detected
    case  TBIV_TBCCR1:
        if (!Count_P41)
                  {
                  // TBCCR1 = TBR; // Done automatically at ISR
                  R2Edge1 = TBCCR1;
                  Count_P41++;
                  }
              else
                  {
                  R2Edge2 = TBCCR1;
                  Count_P41=0x0;
                  }
        TBCCTL1 &= ~CCIFG;
      break;
    case  TBIV_TBCCR2:
        TBCCTL2 &= ~CCIFG;
        break;
    case  TBIV_TBCCR3:
            TBCCTL3 &= ~CCIFG;
            break;
    case  TBIV_TBCCR4:
            TBCCTL4 &= ~CCIFG;
            break;
    case  TBIV_TBCCR5:
            TBCCTL5 &= ~CCIFG;
            break;
    case  TBIV_TBCCR6:
            TBCCTL6 &= ~CCIFG;
            break;
    //Overflow in Timer B detected
    case TB0IV_TBIFG:
       overflow_count++; //Increment a 16 bit variable to get a 32bit timer
       TBCCTL0 &= ~CCIFG;
       TBCTL &= ~0x1;
       break;
    default : break;
  }
  TBCTL &= ~0x1;
}