MSP430F54xx clock and serial/I2C baud rate

Hi to all, I am new to this website.

I am pretty new also with the MSP430 architecture.

I would like to ask you if there's a method of dinamically changing the MSP430F54xx clock on demand,

(i.e. from 4MHz to 8 MHz and so on)

while leaving the clock and baud rate af Serials, UARTs and I2Cs unchanged.

With my code, changing the microprocessor clock also affects Serial clock and, of course, baud rate

Here's the code I use to start the core clock

(taken from MSP430F5XXX evaluation board software)

/*X1 START*/

// Set up XT1 Pins to analog function, and to lowest drive    
  P7SEL |= 0x03;  
  UCSCTL6 |= XCAP_3 ;                       // Set internal cap values (12pF)
 
  while ( (SFRIFG1 & OFIFG))              // Check OFIFG fault flag
  {// Clear OSC fault flags
    UCSCTL7 &= ~(DCOFFG + XT1LFOFFG + XT1HFOFFG + XT2OFFG);
    SFRIFG1 &= ~OFIFG;                    // Clear OFIFG fault flag
  }
  UCSCTL6 &= ~(XT1DRIVE1+XT1DRIVE0);    
  // Reduce the drive strength to 00  

(.....)

/*MICROPROCESSOR CLOCK START*/

__bis_SR_register(SCG0);                  // Disable the FLL control loop    
  UCSCTL0 = 0x00;                           // Set lowest possible DCOx, MODx
  UCSCTL1 = SYSCLK_4MHZ;                    // Select suitable range (4 MHz)
 
  UCSCTL2 = setMultiplier + FLLD_1;         // Set DCO Multiplier
  UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV  |  SELM__DCOCLKDIV ;
  __bic_SR_register(SCG0);                  // Enable the FLL control loop
 
  // Loop until XT1,XT2 & DCO fault flag is cleared
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
 
  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_FLL_reference. See UCS chapter in 5xx UG
  // for optimization.
  // 32 x 32 x / f_FLL_reference (32,768 Hz) = .03125 = t_DCO_settle
  // t_DCO_settle / (1 / 25 MHz) = 781250 = counts_DCO_settle
  __delay_cycles(781250);  
 

(..)

/* I2C clock start on UCB3*/

 UCB3CTL1 |= UCSWRST;                      // force reset state for I2C
  UCB3CTL0 = UCMST + UCMODE_3 + UCSYNC;     // I2C Master, synchronous mode
  UCB3CTL1 = UCSSEL_2 + UCSWRST;            // Use SMCLK   
  UCB3BRW=0x01FF;