For a long time, I have had an interest in FPGA development. You can find boards that come with a JTAG programmer on ebay for less than $20. The following ebay link shows a board similar to the one I had purchased http://www.ebay.com/itm/361568712810 I experimented with it a lot for a while and then I probably got distracted by some new TI toy 
Occasionally, I would pick it up and try different things with it. However, the cost and form factor of the chips discourages me from doing anything real with it. For me these things are more of an educational plaything.
Yesterday, I noticed the neo430 project on opencores.org. It is an msp430 compatible processor implemented in VHDL. It didn't take me long to get it installed and it actually seems to work pretty well. There are some difference between the neo430 and the msp430. ( see list below for the details ) Using the Altera Cyclone II EP2C5 board I linked above I was able to use the example code to create an msp430 like device with 4K of ROM and 4K of RAM. It runs a serial bootloader over its UART peripheral and allows you to toggle the pins using its parallel port peripheral. It has a simple timer peripheral. It has its own custom peripherals and 'C' header files setup to access those. It comes all setup to use msp430-gcc as a development tool with the device you create.
The instructions are pretty complete neo430 instructions , I just followed them to get started. For my Altera chip, I used the free web edition of quartus II 13.0.1 sp1 to convert the VHDL code into a loadable bitstream. Once you load that on to the FPGA chip using the USB-Blaster, a serial terminal is used to interact with the bootloader and upload msp430-gcc compiled files. The provided makefiles automate the msp430 code creation process. I'm using this on linux and I had to make a few changes to point at the directory where my msp430-gcc is installed. If you are windows user it will probably just work out of the box for you.
I'll try and post more on my experiments. In the meantime, I thought others might find it interesting.
Functional Diagram:
Memory Layout:
Since the NEO430 is not intended as MSP430 clone. Hence, there are several crucial differences to TI's
original architecture, so existing programs must be modified and re-compiled to successfully run on the
NEO430. The major differences are:
✗ Completely different processor modules with different functionality (except for MAC unit)
✗ Maximum of 32kB IMEM and 28kB DMEM
✗ Specific memory map – custom NEO430 linker script and compilation script required
✗ Just 4 CPU interrupt channels (instead of 16)
✗ Single clock domain for complete processor
✗ Different numbers of cycles for instruction execution required
✗ Only one power-down (sleep) mode
✗ Wishbone-compatible interface to attach custom IP (e.g. modules from opencores.org)
✗ Internal bootloader with text interface (via serial port / UART)
-rick